A field programmable device (or a so-called field programmable gate array or "FPGA") is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a field programmable device, the user configures an on-chip interconnect structure of the field programmable device so that selected inputs and selected outputs of selected on-chip logic components are connected together in such a way that the resulting circuit is the user-specific circuit desired by the user.
FIG. 1A is a top down simplified diagram illustrating a corner portion of a field programmable device. Sides S1, S2 and S3 are three sides of the die of the field programmable device. A plurality of antifuses L1-L25 are programmable so that the digital circuitry contained in modules M1-M8 can be connected together to realize user-specific circuits. In contrast to "fuses" conventionally used in programmable read only memory devices (PROMs) or programmable logic devices (PLDs) which are conductive before being blown and are nonconductive after being blown, "antifuses" such as the antifuses shown in FIG. 1A are nonconductive before being programmed and are conductive after being programmed.
FIG. 1B is a cross sectional view of an antifuse of FIG. 1A, such as antifuse L1. Antifuse L1 comprises a thin dielectric body layer 121 and a layer of diffusible conductive material 122 sandwiched between a horizontal wire W12 and a vertical wire W13 so that a first surface portion 126 of the antifuse contacts vertical wire W13 and so that a second surface portion contacts horizontal wire W12. The horizontal wire W12 may, for example, be located on a first metallization layer of the programmable device whereas the vertical wire W13 may be located on a second metallization layer of the programmable device. An insulating layer 128 may be disposed between the first metallization layer and the second metallization so that the antifuse forms a via-like structure from the vertical wire W13 down to the horizontal wire W12. In its unprogrammed state, horizontal wire W13 is insulated from vertical wire W13 by dielectric body layer 121. In its programmed state, a conductive path 129 is formed through body layer 121 so that horizontal wire W12 and vertical wire W13 are substantially electrically connected. Such an antifuse which can be programmed to connect two orthogonally oriented wires is called a "cross" antifuse; whereas an antifuse which can be programmed to connect two adjacent ends of two collinear wires is called a "pass" antifuse. Antifuses L1, L2, L5, L6, L9, L10, L13, and L19-L25 in FIG. 1A are cross antifuses. Antifuses L14, L16, L3, L4, L17, L7, L8, L18, L11 and L12 in FIG. 1A are pass antifuses.
If, for example, the circuit shown in FIG. 2A is to be realized in the corner portion of the field programmable device of FIG. 1A, flip-flop FF2 in module M3 of FIG. 1A may serve as flip-flop 21 of FIG. 2A, whereas AND gate AND2 in module M4 of FIG. 1A may serve as AND gate 22 of FIG. 2A. By programming antifuses L9, L12, and L13 to be conductive, a net is established extending from the output of flip-flop FF2 to a non-inverting input of AND gate AND2. This net corresponds with the net 23 of FIG. 2A.
Accordingly, an electrical connection is made from an output of flip-flop FF2, to horizontal wire W1, through programmed cross antifuse L9, to vertical wire W2, through programmed pass antifuse L12, to vertical wire W21, through programmed cross antifuse L13, to horizontal wire W3, and to a non-inverting input of AND gate AND2. Transistors T1-T8 are turned off during normal circuit operation so none of wires W4-W11 is connected to the net between flip-flop FF2 and AND gate AND2.
The circuit shown in FIG. 2B having a larger net 24 may also be realized in the corner portion of the field programmable device of FIG. 1A. The flip-flop FF1 in module M1 of FIG. 1A may serve as flip-flop 25 of FIG. 2B, the AND gate AND1 in module M2 of FIG. 1 may serve as AND gate 26 of FIG. 2B, the output buffer B1 and pad P1 of FIG. 1A may serve as the first output buffer 27 and pad 28 of FIG. 2B, and the output buffer B2 and pad P2 of FIG. 1A may serve as the second output buffer 29 and pad 30 of FIG. 2B. To realize this larger net 24 in the field programmable device of FIG. 1A, seven antifuses L1-L7 are programmed to be conductive.
Accordingly, an electrical connection is made from an output of flip-flop FF1, to horizontal wire W12, through programmed cross antifuse L1, to vertical wire W13, through programmed cross antifuse L2, to horizontal wire W14, through programmed pass antifuse L3, to horizontal wire W15, and to output buffer B1 and pad P1. This net also extends from vertical wire W13, through programmed pass antifuse L4, to vertical wire W16, through programmed cross antifuse L5, to horizontal wire W17, and to a non-inverting input of AND gate AND1. This net also extends from vertical wire W16, through programmed cross antifuse L6, to horizontal wire W18, through programmed pass antifuse L7, to horizontal wire W19, and to output buffer B2 and pad P2. The two above described nets are disconnected from each other during normal circuit operation after antifuse programming because pass antifuse L8 is not programmed and because pass transistors PT1-PT10 are not turned on during normal circuit operation.
Such nets of a user-specific circuit may be realized in a field programmable device using the following method. First, the various gates and other circuitry of the user-specific circuit are "placed" in the various modules of a field programmable device. A flip-flop FF2 corresponding with flip-flop 21 of FIG. 2A is, for example, placed in module M3 whereas the AND gate AND2 corresponding with AND gate 22 is placed in module M4. Second, the nets of the user-specific circuit are "routed" between modules so that the antifuses to be programmed can be identified. In the above-described example, a net corresponding with connection 23 of FIG. 2A is routed through wire W1, antifuse L9, wire W2, L12, W21 antifuse L13, and wire W3. Third, a program sometimes called a "sequencer" is used to determine the order in which the antifuses in the routed nets will be programmed and the method by which each of those antifuses will be programmed.
A list of all the antifuses to be programmed for realizing a given user-specific circuit is typically supplied to the sequencer. From this list, the sequencer generates an ordered list indicating: 1) the sequence in which the antifuses are to be programmed, and 2) which of the pass transistors PT1-PT10 and which of the program drivers PD1-PD9 of the field programmable device are to be turned on and which are to be turned off to program each of the antifuses in the sequence. If, for example, cross antifuse L1 is to be programmed, a first programming driver PD8 may be controlled to drive a vertical wire W20 with a programming voltage (Vpp) and a second programming drive PD1 may be controlled to drive a horizontal wire W4 with a ground voltage. Because transistors T1 and PT1 are controlled to be turned on, a programming voltage between vertical wire W13 and horizontal wire W12 is dropped across antifuse L1. Antifuse L1 is thereby programmed to be permanently conductive. The order of programming of the antifuses is particularly important because programming certain antifuses first may render it impossible to program other of the antifuses later. Accordingly, the sequencer outputs a programming sequence which allows the programming of all the antifuses to be programmed.
Special wires having no pass transistors or pass antifuses called express wires may also be provided to provide low impedance programming access deep into the interconnect matrix of wires. One such express wire EW1 is shown in FIG. 1A running vertically and being connected to programming driver PD10.
The above described method of placing circuitry in the various modules of the field programmable device, routing nets, and determining how antifuses in the nets are to be programmed is, in some embodiments, an iterative process. Before the final realization of the user-specific circuit is determined, multiple placements may be tried, multiple net configurations may be tried with a given placement, and multiple programming sequences and programming methods may be tried using a given net configuration.
When such a place, route and sequence method is used to realize a user-specific circuit in a program field programmable device, however, reliability problems are sometimes encountered. Some field programmable devices programmed to have large nets fail, whereas other field programmable devices programmed which are programmed to have no large nets do not fail.